1. Purpose of Thinning
In the semiconductor manufacturing process, wafers must maintain a certain thickness during the front-end-of-line (FEOL) stages to ensure structural stability, prevent warping or deformation, and facilitate handling during fabrication. The starting thickness varies by wafer diameter: approximately 520 μm for 4-inch, 670 μm for 6-inch, 725 μm for 8-inch, and 775 μm for 12-inch wafers. Although the functional layers of chips are formed within only a few micrometers of the wafer surface, the full thickness is beneficial for supporting complex process steps. Thinning is performed later, during the packaging stage.
Thinning wafers for packaging addresses several key considerations. From a dicing perspective, thicker wafers are harder and more prone to uneven cuts, chipping, or cracking during mechanical blade dicing, which increases yield loss. Thinned wafers, being less rigid, allow for more precise and efficient die separation, significantly improving dicing quality and throughput. As electronic devices trend toward miniaturization, package thickness is critical. Thinning enables thinner packages, especially for chip stacking technologies, meeting the demands of wearables, mobile devices, and other compact products. Furthermore, an oxide layer formed on the wafer backside during manufacturing can adversely affect die bonding quality. The thinning process removes this layer, providing a clean, flat surface for reliable electrical connections. Additionally, thinning shortens the heat dissipation path, improving thermal performance, preventing performance degradation from overheating, and enhancing long-term reliability.
Different package types require specific final thicknesses. For DIP packages, wafers are typically thinned to about 300 μm; for BGA packages, the range is 120–250 μm; and in advanced 3D stacking packages, die thickness can be reduced to below 30 μm for high-density integration.
In conventional dicing, a blue tape is first laminated onto the wafer backside, and the wafer is mounted on a metal frame. Separation is then achieved via mechanical sawing or laser cutting. Mechanical dicing uses a high-speed rotating diamond blade but can induce stress and cause chipping. Laser cutting focuses a laser beam to create a modified layer within the wafer, enabling die separation with tape expansion, which minimizes damage to the silicon.
Process innovations have led to techniques like Dicing Before Grinding (DBG) and Dicing By Thinning (DBT). In DBG, partial-depth grooves are first cut on the wafer front side, followed by backside grinding. DBT involves forming similar grooves, then grinding the backside, and finally using a process like ADPE (Atmospheric Downstream Plasma Etching) to remove the remaining material, enabling automatic die separation. These methods effectively avoid wafer warpage from thinning and edge damage from dicing. DBT, utilizing isotropic silicon etchants, can remove grinding-induced damage and even repair micro-cracks and grooves, significantly improving die strength. The evolved DBG plus DAF (Die Attach Film) process further enhances alignment accuracy by laminating DAF onto the thinned wafer backside and performing separate laser cutting of the DAF, representing a key advancement in advanced packaging.
2. Major Thinning Techniques
Various backside thinning techniques exist for silicon wafers, primarily including grinding, lapping, dry polishing, chemical mechanical polishing (CMP), wet chemical etching, plasma-enhanced chemical etching (PECE), and atmospheric downstream plasma etching (ADPE).
Wafer Grinding: This process uses a rotating grinding wheel to apply pressure, causing surface damage and fracture to remove material. Its advantages are high efficiency, good post-thinning flatness, and relatively low cost. A significant drawback is the formation of a damaged layer several micrometers deep, which can reduce device reliability, leave residual stress, and cause wafer warpage. Subsequent processes are often required to remove this damage layer.
Wafer Lapping: Generally performed at low speed using loose abrasive slurry, lapping results in a matte surface with tiny pits. Compared to grinding, lapping applies lower pressure, uses free abrasives, and has a lower material removal rate.
Chemical Mechanical Polishing (CMP): This process combines mechanical, chemical, or electrochemical action to reduce surface roughness, producing a smooth, mirror-like finish. It's a "wet" process using fine micron or sub-micron abrasive particles in a slurry held by a pad, removing material on a micron scale. It requires a pre-processed surface with low roughness. While excellent for improving flatness and reducing defects, CMP has low throughput and high cost.
Dry Polishing: Similar in principle to grinding but uses a polishing wheel made of fibers and metal oxides instead of a diamond wheel. It can remove shallow grinding damage and achieve nano- or sub-nanometer surface finishes at a lower cost. However, its slow processing speed makes it suitable only for removing thin damaged layers, not for bulk material removal.
Wet Chemical Etching: Thinning is achieved via chemical reaction between the wafer and an etchant, such as acidic mixtures (nitric/acetic/hydrofluoric acids) or alkaline solutions (e.g., potassium hydroxide). The advantage is an undamaged, dislocation-free surface, improving wafer strength and reducing warpage. However, it requires protecting the wafer frontside from etchant attack and has limited ability to correct grinding marks, restricting its standalone use for complex surfaces.
Atmospheric Downstream Plasma Etching (ADPE): A pure chemical, dry etching technique operating at atmospheric pressure. Using argon as a carrier gas, CF₄ is ionized and decomposed. Fluorine radicals react with silicon to form volatile SiF₄, removing material. It doesn't require frontside protection, making it suitable for thin wafers and those with bump structures. It effectively removes grinding damage, can remove 50–100 μm of material, and provides better surface uniformity than wet etching. Drawbacks include high equipment cost and stringent process control requirements.
In practice, combination processes balance efficiency and precision. For example, to thin a wafer from 300 μm to 120 μm, high-speed grinding might first remove most material down to ~160 μm, leaving a damaged surface. Subsequent fine processing—using CMP, wet etching, ADPE, or dry polishing—is then chosen based on product requirements.
Common combinations include "Backside Grinding + CMP," "Backside Grinding + Wet Etching," "Backside Grinding + ADPE," and "Backside Grinding + Dry Polishing." "Grinding + CMP" is suited for applications needing ultra-smooth surfaces (nanoscale roughness), while "Grinding + ADPE" is advantageous for ultra-thin wafers with delicate microstructures, ensuring both efficiency and structural integrity.
3. Grinding-Based Thinning
Grinding-based thinning is the core solution for wafer thinning due to its high material removal rate, excellent control over surface flatness, and cost-effectiveness.
3.1. Evolution of Wafer-Rotation Grinding Technology
The development of thinning technology reflects the industry's pursuit of higher precision and efficiency. Early rotary table grinding was used for smaller wafers (<100 mm diameter), but its limitations in throughput and thickness uniformity became apparent with larger wafers. In 1988, Matsui et al. proposed wafer-rotation grinding, offering a new approach for ultra-thinning large-diameter wafers.
This technology synchronizes the wafer's rotation with the grinding wheel's motion for efficient material removal and precise surface control. For instance, a 300 mm wafer with an initial thickness of 750 μm can be thinned to 180 μm in about 90 seconds using this method, achieving thickness uniformity within ±0.3 μm and a surface roughness (Ra) as low as 2–4 nm, meeting stringent requirements for advanced chips.
However, the beveled edge of wafers is prone to chipping during grinding. The TAIKO process addresses this by using a special protective ring on the chuck to preserve an approximately 3 mm wide rim on the wafer edge during grinding. This enhances the mechanical strength of thin wafers, reduces breakage risk, and significantly mitigates warpage.
3.2. Grinding-Based Thinning Process Flow
1) Protective Taping of Wafer Frontside: Protecting the delicate circuits and devices on the wafer frontside before backside grinding is critical. This is typically done using a tape laminator. The wafer is placed frontside up on the stage. Protective tape is dispensed from a roll, laminated onto the wafer surface via rollers for uniform adhesion, and then trimmed along the wafer edge. The taped wafer is stored in a cassette.
The protective tape consists of a base film and an adhesive layer. Based on debonding methods, tapes are categorized as, for example, UV-release type (adhesive loses tack under UV exposure) or thermal-release type (adhesive softens upon heating), the latter being used for UV-sensitive devices.
2) Backside Grinding Process: The taped wafer is transferred to a grinding machine's ceramic porous vacuum chuck, which holds the wafer via suction and rotates it at high speed. A grinding wheel, under precise servo control, contacts the wafer backside at a set pressure and rotation speed.
The process involves two stages: coarse grinding and fine grinding. Coarse grinding uses a large-grit wheel for high removal rates. Fine grinding employs a finer-grit wheel to refine the surface, reducing roughness and improving flatness. This two-step approach balances speed with surface quality.
3) Protective Tape Removal: After grinding, the wafer is cleaned and dried to remove debris and coolant. The tape is then removed according to its type: UV exposure for UV-release tape or heating for thermal-release tape.
For debonding, the wafer is placed frontside up on a removal stage. A sticky peeling tape is used to lift off the protective tape. The entire process is conducted in an ionized air environment to prevent electrostatic discharge damage. As wafer thickness decreases, mechanical strength diminishes, making them more susceptible to damage. Therefore, tape removal requires careful control of force and environmental conditions to ensure wafer integrity.
Cersol offers Vacuum Chucks for wafer thinning and CMP Polishing Discs. Please feel free to contact us!
